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general description the max15003 is a triple-output, pulse-width-modulat- ed (pwm), step-down dc-dc controller with tracking and sequencing capability. the device operates over the input voltage range of 5.5v to 23v or 5v 10%. each pwm controller provides an adjustable output down to 0.6v and delivers up to 15a for each output with excellent load and line regulation. the max15003 is optimized for high-performance, small-size power management solutions. the options of coincident tracking, ratiometric tracking, and output sequencing allow the tailoring of the power- up/power-down sequence depending on the system requirements. each of the max15003 pwm sections uti- lizes a voltage-mode control scheme with external com- pensation allowing for good noise immunity and maximum flexibility with a wide selection of inductor val- ues and capacitor types. each pwm section operates at the same, fixed switching frequency that is program- mable from 200khz to 2.2mhz and can be synchro- nized to an external clock signal using the sync input. each converter operating at up to 2.2mhz with 120 out-of-phase, increases the input capacitor ripple fre- quency up to 6.6mhz, thereby reducing the rms input ripple current and the size of the input bypass capaci- tor requirement significantly. the max15003 includes internal input undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of each convert- er. the power-on reset ( reset ) with an adjustable timeout period monitors all three outputs and provides a reset signal to the processor when all outputs are within regulation. protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. the max15003 is available in a space-saving, 7mm x 7mm, 48-pin tqfn-ep package and is specified for operation over the -40c to +125c automotive temper- ature range. see the max15002 data sheet for a dual version of the max15003. applications pci express ? host bus adapter power supplies networking/server power supplies point-of-load dc-dc converters features 5.5v to 23v or 5v ?0% input voltage range triple-output synchronous buck controller selectable in-phase or 120 out-of-phase operation output voltages adjustable from 0.6v to 0.85v in lossless valley-mode current sensing or accurate valley current sensing using r sense external compensation for maximum flexibility digital soft-start and soft-stop sequencing or coincident/ratiometric v out tracking individual pgood outputs reset output with a programmable timeout period 200khz to 2.2mhz programmable switching frequency external frequency synchronization hiccup mode short-circuit protection space-saving (7mm x 7mm) 48-pin tqfn package ordering information 19-1048; rev 1; 8/12 pci express is a registered trademark of pci-sig corporation. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. max15003 triple-output buck controller with tracking/sequencing evaluation kit available pin configuration appears at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. note: devices are also available in a tape-and-reel packaging. specify tape and reel by adding t to the part number when ordering. tape-and-reel orders are available in 2.5k incre- ments. part temp range pin-package max15003atm+ -40c to +125c 48 tqfn-ep* (7mm x 7mm)
max15003 triple-output buck controller with tracking/sequencing 2 maxim integrated absolute maximum ratings electrical characteristics (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg _ = v reg , v pgnd _ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim _ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v and t a = t j = +25c, unless otherwise noted.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, lx_, csn_ to sgnd..........................................-0.3v to +30v bst_ to sgnd ........................................................-0.3v to +30v bst_ to lx_ ..............................................................-0.3v to +6v reg, dreg_, sync, en_, rt, ct, reset , phase, sel to sgnd ...............................-0.3v to +6v ilim_, pgood_, fb_, comp_, csp_ to sgnd .......-0.3v to +6v dl_ to pgnd_.......................................-0.3v to (v dreg_ + 0.3v) dh_ to lx_ ...............................................-0.3v to (v bst_ + 0.3v) pgnd_ to sgnd, pgnd_ to any other pgnd_.......-0.3v to +0.3v continuous power dissipation (t a = +70c) 48-pin tqfn (derate 38.5mw/c above +70c) .......3076.9mw* operating junction temperature range ...........-40c to +125c junction temperature ......................................................+150c storage temperature range .............................-60c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units system specifications 5.5 23.0 v input voltage range v in v in = v reg = v dreg_ (note 2) 4.5 5.5 v input undervoltage lockout threshold v uvlo v in rising 3.95 4.05 4.15 v input undervoltage lockout hysteresis 0.35 v operating supply current v in = 12v, v fb_ = 0.8v, no switching 5 8 ma shutdown supply current v in = 12v, en_ = 0v, pgood_ unconnected 150 300 a reg voltage regulator output-voltage setpoint v reg v in = 5.5v to 23v 4.9 5.2 v load regulation i reg = 0 to 120ma, v in = 12v 0.2 v digital soft-start/soft-stop soft-start/soft-stop duration 2048 clocks reference voltage steps 64 steps error transconductance amplifier fb_, track_ input bias current -250 +250 na t a = t j = 0c to +85c 0.5945 0.6 0.6065 v fb_ voltage setpoint v fb t a = t j = -40c to +125c 0.590 0.6 0.608 v package thermal characteristics (note 1) 48 tqfn junction-to-ambient thermal resistance ( ja )...............26c/w junction-to-case thermal resistance ( jc )......................1.3c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . * as per jedec51 standard (multilayer board).
max15003 triple-output buck controller with tracking/sequencing 3 maxim integrated parameter symbol conditions min typ max units fb_ to comp_ transconductance 2.1 ms comp_ output swing 0.75 3.50 v open-loop gain 80 db unity-gain bandwidth 10 mhz drivers dl_, dh_ break-before-make time c load = 5nf 20 ns low, sinking 100ma 0.9 dh1 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dh2 on-resistance high, sourcing 100ma 0.3 ? low, sinking 100ma 0.9 dh3 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dl1 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dl2 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dl3 on resistance high, sourcing 100ma 1.3 ? lx_ to pgnd_ on-resistance sinking 10ma 8 ? current-limit and hiccup mode cycle-by-cycle valley current- limit adjustment range v cl v cl_ = v ilim_ / 10 50 300 mv v ilim_ = 0.5v 44 54 cycle-by-cycle valley current- limit threshold tolerance v ilim_ = 3v 290 310 mv ilim_ reference current v ilim_ = 0 to 3v, t a = t j = +25c 20 a ilim_ reference current temperature coefficient 3333 ppm/c csp_, csn_ input bias current v csp_ = 0v, v csn_ = -0.3v -20 +20 a number of cumulative current- limit events to hiccup n cl 8 number of consecutive non- current-limit cycles to clear n cl n clr 3 hiccup timeout 4096 clock periods enable/phase/sel en_ threshold v enCth en_ rising 1.19 1.215 1.24 v en_ threshold hysteresis 0.12 v en_ input bias current -1 +1 a electrical characteristics (continued) (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg _ = v reg , v pgnd _ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim _ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v and t a = t j = +25c, unless otherwise noted.) (note 1)
max15003 triple-output buck controller with tracking/sequencing 4 maxim integrated electrical characteristics (continued) (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg _ = v reg , v pgnd _ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim _ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v and t a = t j = +25c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units phase input logic high 2v phase input logic low 0.8 v phase input bias current -1 +1 a sel high threshold 80 %v reg sel low threshold 20 %v reg sel input bias current present only during startup -100 +100 a pgood, reset outputs fb_ for threshold pgood_ fb_ falling 0.540 0.555 0.570 v reset , pgood_ output low level sinking 3ma 0.1 v reset , pgood_ leakage -1 +1 a ct charging current 1.8 2.0 2.2 a ct pulldown resistance sinking 3ma 33 ? ct rising 1.8 2.6 ct threshold for reset delay ct failling 1.2 v oscillator switching frequency range (each converter) f sw v sync = 0v, f clk = 10 11 / (r rt + 1.75k ? ) 200 2200 khz f sw 1500khz -5 +5 switching frequency accuracy (each converter) f sw 1500khz -7 +7 % v phase = 0v (dh1 rising to dh2 rising and dh2 rising to dh3 rising) 120 degrees phase delay v phase = v reg (dh1 rising to dh2 rising and dh2 rising to dh3 rising) 0 degrees rt voltage v rt 40k ? < r rt < 500k ? 2v minimum controllable on-time t on ( min ) 75 ns minimum off-time t off ( min ) 150 ns sync high-level voltage 2v sync low-level voltage 0.8 v sync internal pulldown resistor 50 100 200 k ? sync frequency range (note 3) 0.6 6.9 mhz sync minimum on-time 30 ns sync minimum off-time 30 ns pwm ramp amplitude (peak-to-peak) 2v pwm ramp valley 1v note 1: 100% production tested at t a = t j = +25c and t a = t j = +125c. limits at other temperature are guaranteed by design. note 2: for 5v applications, connect reg directly to in. note 3: the switching frequency is 1/3 of the sync frequency.
converter 1 efficiency vs. load current max15003 toc01 load current (a) efficiency (%) 1 50 60 70 80 90 100 40 0.1 10 v in = 6v v in = 12v v in = 16v v out1 = 3.3v f sw = 600khz converter 2 efficiency vs. load current max15003 toc02 load current (a) efficiency (%) 1 50 60 70 80 90 100 40 20 30 10 0 0.1 10 v in = 6v v in = 12v v in = 16v v out2 = 2.5v f sw = 600khz converter 3 efficiency vs. load current max15003 toc03 load current (ma) efficiency (%) 1 50 60 70 80 90 100 40 20 30 10 0 0.1 10 v in = 6v v in = 12v v in = 16v v out3 = 1.2v f sw = 600khz converter 1 load regulation max15003 toc04 load current (ma) output voltage accuracy (%) 1500 0 0.25 0.50 0.75 1.00 -0.25 -0.50 -0.75 -1.00 0 2000 500 2500 1000 3000 v out1 = 3.3v converter 2 load regulation max15003 toc05 load current (ma) output voltage accuracy (%) 3000 0 0.25 0.50 0.75 1.00 -0.25 -0.50 -0.75 -1.00 0 4000 1000 5000 2000 6000 v out2 = 2.5v converter 3 load regulation max15003 toc06 load current (ma) output voltage accuracy (%) 6000 0 0.25 0.50 0.75 1.00 -0.25 -0.50 -0.75 -1.00 0 8000 2000 4000 10,000 v out3 = 1.2v typical operating characteristics (figure 8, v in = 12v, c reg = 2.2f, t a = +25c, unless otherwise noted.) max15003 triple-output buck controller with tracking/sequencing 5 maxim integrated internal voltage regulation (reg) max15003 toc07 i reg (ma) v reg (v) 60 4.95 4.97 4.96 4.98 4.99 5.00 4.94 4.93 4.92 4.91 4.90 080 20 40 100 v in = 12v c reg = 2.2 f converter_ switching frequency vs. r rt max15003 toc08 r rt (k ? ) switching frequency (khz) 300 400 1000 10,000 100 0 0 500 100 200 600
typical operating characteristics (continued) (figure 8, v in = 12v, c reg = 2.2f, t a = +25c, unless otherwise noted.) switching frequency accuracy vs. temperature max15003 toc09 temperature ( c) switching frequency accuracy (khz) 50 100 75 10 8 6 4 2 0 -2 -4 -6 -8 -10 -50 125 -25 0 25 150 f sw = 600khz valley current-limit threshold vs. v ilim max15003 toc10 v ilim (mv) valley current-limit threshold (mv) 2000 2500 350 300 250 200 150 100 50 500 3000 1000 1500 3500 valley current-limit threshold vs. temperature max15003 toc11 temperature ( c) valley current-limit threshold (mv) 50 25 75 100 90 80 70 60 50 40 30 20 -50 100 125 -25 0 150 r ilim = 25.5k ? temperature coefficient (nom.) = 3,333ppm/ c switching current vs. frequency max15003 toc12 frequency (khz) switching current (ma) 1200 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 200 1700 700 2200 ratiometric startup max15003 toc13 1ms/div 10v/div 1v/div 1v/div 1v/div 0v v out1, 2, 3 v in v en2 = v en3 = 0v, sel = reg ratiometric shutdown max15003 toc14 400 max15003 triple-output buck controller with tracking/sequencing 6 maxim integrated channel 2 short circuit (ratiometric mode) max15003 toc15 400 channel 1 short circuit (ratiometric mode) max15003 toc16 400
typical operating characteristics (continued) (figure 8, v in = 12v, c reg = 2.2f, t a = +25c, unless otherwise noted.) max15003 triple-output buck controller with tracking/sequencing 7 maxim integrated channel 2 short circuit (coincident mode) max15003 toc19 400 channel 1 short circuit (coincident mode) max15003 toc20 400 sequencing startup max15003 toc21 1ms/div 1v/div 0v 1v/div 1v/div 10v/div 0v v in v out1, 2, 3 sel = reg sequencing shutdown max15003 toc22 400 coincident startup max15003 toc17 1ms/div 1v/div 10v/div 1v/div 1v/div 0v 0v v out1, 2, 3 v in circuit of figure 8, sel = reg coincident shutdown max15003 toc18 400
max15003 triple-output buck controller with tracking/sequencing 8 maxim integrated typical operating characteristics (continued) (figure 8, v in = 12v, c reg = 2.2f, t a = +25c, unless otherwise noted.) reset at shutdown (sequencing mode) max15003 toc25 400 s/div 1v/div 1v/div 1v/div 5v/div 0v 0v v out1 v out2 v out3 v reset en/track2 = pgood1 en/track3 = pgood2 sel = gnd converter 1 short-circuit condition (hiccup mode) max15003 toc26 1ms/div 10v/div 10a/div 1v/div 500mv/div 5v/div v out1 i out1 v lx1 v dl1 v pgood1 converter 1 output short-circuit (sequencing mode) max15003 toc27 400 s/div 1v/div 1v/div 10v/div 2v/div 0v 0v 0v v out1 v out2 v out3 v in en/track2 = pgood1 en/track3 = pgood2 sel = gnd converter 2 output short-circuit (sequencing mode) max15003 toc28 400 s/div 2v/div 1v/div 10v/div 2v/div 0v 0v 0v v out1 v out2 v out3 v in en/track2 = pgood1 en/track3 = pgood2 sel = gnd channel 1 output short circuit (sequencing mode) max15003 toc23 400 s/div 1v/div 1v/div 10v/div 2v/div 0v 0v 0v 0v v out3 v out1 v in v out2 sel = gnd en/track2 = pgood1 en/track3 = pgood2 reset at startup (sequencing mode) max15003 toc24 20ms/div 1v/div 1v/div 1v/div 5v/div 0v 0v v out1, 2, 3 en/track2 = pgood1 en/track3 = pgood2 v reset sel = gnd
max15003 triple-output buck controller with tracking/sequencing 9 maxim integrated typical operating characteristics (continued) (figure 8, v in = 12v, c reg = 2.2f, t a = +25c, unless otherwise noted.) converter 3 output short-circuit (sequencing mode) max15003 toc29 400 s/div 2v/div 1v/div 10v/div 1v/div 0v 0v 0v v out1 v out2 v out3 v in en/track2 = pgood1 en/track3 = pgood2 sel = gnd 120 out-of-phase operation max15003 toc30 400ns/div 10v/div 10v/div 5v/div 10v/div 0v 0v 0v 0v v lx2 v lx3 v lx1 v sync sel = gnd in-phase operation max15003 toc31 400ns/div 10v/div 10v/div 5v/div 10v/div 0v 0v 0v 0v v lx2 v lx3 v lx1 v sync sel = gnd break-before-make timing max15003 toc32 20ns/div 2v/div 5v/div 0v 0v v dl1 v lx1 load-transient response (i out3 = 100ma to 10a) max15003 toc33 200 load-transient response (i out3 = 5a to 10a) max15003 toc34 200
max15003 triple-output buck controller with tracking/sequencing 10 maxim integrated pin description pin name function 1ct reset timeout capacitor connection. connect a timing capacitor from ct to sgnd to set the reset delay. ct sources 2a into the timing capacitor. when the voltage at ct passes 2v, open-drain reset goes high impedance. 2in supply input connection. connect to an external voltage source from 5.5v to 23v. for 4.5v to 5.5v input application, connect in and reg together. 3 reg 5v regulator output. bypass with a 2.2f ceramic capacitor to sgnd. 4 sel track/sequence select input. connect sel to reg to configure as a triple tracker at startup or connect sel to sgnd to configure as a triple sequencer or leave sel unconnected to configure as a dual tracker and independent sequencer. note: when configured as a triple sequencer, each rail is independently enabled using the en_. 5 pgnd1 controller 1 power-ground connection. connect the input filter capacitors negative terminal, the source of the synchronous mosfet, and the output filter capacitors return to pgnd1. connect externally to sgnd at a single point near the input capacitor return terminal. 6 dl1 controller 1 low-side gate driver output. dl1 is the gate driver output for the synchronous mosfet. 7 dreg1 controller 1 low-side gate driver supply. connect externally to reg and the anode of the boost diode. connect a minimum of 0.1f ceramic capacitor from dreg1 to pgnd1. 8 lx1 controller 1 high-side mosfet source connection/synchronous mosfet drain connection. connect the inductor and the negative side of the boost capacitor to lx1. 9 dh1 controller 1 high-side gate driver output. dh1 drives the gate of the high-side mosfet. 10 bst1 controller 1 high-side gate driver supply. connect bst1 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 11 csn1 controller 1 negative current-sense input. connect csn1 to the synchronous mosfet drain (connected to lx1). when using a current-sense resistor, connect csn1 to the junction of a low-side mosfets source and the current-sense resistor. see figure 11. 12 csp1 controller 1 positive current-sense input. connect csp1 to the synchronous mosfet source (connected to pgnd1). when using a current-sense resistor, connect csp1 to the pgnd1 end of the current-sense resistor. 13 ilim1 controller 1 valley current-limit set output. connect a 25k ? to 150k ? resistor, r ilim1 , from ilim1 to sgnd to program the valley current-limit threshold from 50mv to 300mv. ilim1 sources 20a out to r ilim1 . the resulting voltage divided by 10 is the valley current-limit threshold. when using a precision current-sense resistor, connect a resistive divider from reg to ilim1 to sgnd to set the valley current limit. see figure 11. 14 comp1 controller1 error transconductance amplifier output. connect comp1 to the compensation feedback network. 15 en1 controller 1 enable input. en1 must be above 1.24v, v en-th , for the pwm controller to start output 1. controller 1 is the master. use the master as the highest output voltage in a coincident tracking configuration.
max15003 triple-output buck controller with tracking/sequencing 11 maxim integrated pin description (continued) pin name function 16 fb1 controller 1 feedback regulation point. connect to the center tap of a resistive divider from the converter output to sgnd to set the output voltage. the fb1 voltage regulates to v fb (0.6v). 17 pgood1 controller 1 power-good output. open-drain pgood1 output goes high impedance (releases) when fb1 is above 0.925 x v fb = 0.555v. 18 pgnd2 controller 2 power ground connection. connect the input filter capacitors negative terminal, the source of the synchronous mosfet, and the output filter capacitors return to pgnd2. connect externally to sgnd at a single point near the input capacitor return terminal. 19 dl2 controller 2 low-side gate driver output. dl2 is the gate driver output for the synchronous mosfet. 20 dreg2 controller 2 low-side gate driver supply. connect externally to reg and the anode of the boost diode. connect at minimum, a 0.1f ceramic capacitor from dreg2 to pgnd2. 21 lx2 controller 2 high-side mosfet source connection/synchronous mosfet drain connection. connect the inductor and the negative side of the boost capacitor to lx2. 22 dh2 controller 2 high-side gate driver output. dh2 drives the gate of the high-side mosfet. 23 bst2 controller 2 high-side gate driver supply. connect bst2 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 24 csn2 controller 2 negative current-sense input. connect csn2 to the synchronous mosfet drain (connected to lx2). when using a current-sense resistor, connect csn2 to the junction of the low-side mosfets source and the current-sense resistor. see figure 11. 25 csp2 controller 2 positive current-sense input. connect csp2 to the synchronous mosfet source (connected to pgnd2). when using a current-sense resistor, connect csp2 to the pgnd2 end of the current-sense resistor. 26 ilim2 controller 2 valley current-limit set output. connect a 25k ? to 150k ? resistor, r ilim2 , from ilim2 to sgnd to program the valley current-limit threshold from 50mv to 300mv. ilim2 sources 20a out to r ilim2 . the resulting voltage divided by 10 is the valley current-limit threshold. when using a precision current-sense resistor, connect a resistive divider from reg to ilim2 to sgnd to set the valley current limit. see figure 11. 27 comp2 controller 2 error transconductance amplifier output. connect comp2 to the compensation feedback network. 28 en/track2 controller 2 enable/tracking input. see figure 2. when sequencing, en/track2 must be above 1.24v for the pwm controller 2 to start. coincident trackingconnect the same resistive divider used for fb2, from output 1 to en/track2 to sgnd. ratiometric trackingconnect en/track2 to analog ground. 29 fb2 controller 2 feedback regulation point. connect to the center tap of a resistive divider from the converter output to sgnd to set the output voltage. the fb2 voltage regulates to v fb (0.6v). 30 pgood2 controller 2 power-good output. open-drain pgood2 output goes high impedance (releases) when fb2 is above 0.925 x v fb = 0.555v. 31 pgood3 controller 3 power-good output. open-drain pgood3 output goes high impedance (releases) when fb3 is above 0.925 x v fb = 0.555v. 32 fb3 controller 3 feedback regulation point. connect to the center tap of a resistive divider from the converter output to sgnd to set the output voltage. the fb3 voltage regulates to v fb (0.6v).
max15003 triple-output buck controller with tracking/sequencing 12 maxim integrated pin description (continued) pin name function 33 en/track3 controller 3 enable/tracking input. see figure 2. when sequencing, en/track3 must be above 1.24v for the pwm controller 3 to start. coincident trackingconnect the same resistive divider used for fb3, from output 1 to en/track3 to sgnd. ratiometric trackingconnect en/track3 to analog ground. 34 comp3 controller 3 error transconductance amplifier output. connect comp3 to the compensation feedback network. 35 ilim3 controller 3 valley current-limit set output. connect a 25k ? to 150k ? resistor, r ilim3 , from ilim3 to sgnd to program the valley current-limit threshold from 50mv to 300mv. ilim3 sources 20a out to r ilim3 . the resulting voltage divided by 10 is the valley current-limit threshold. when using a precision current-sense resistor, connect a resistive divider from reg to ilim3 to sgnd to set the valley current limit. see figure 11. 36 csp3 controller 3 positive current-sense input. connect csp3 to the synchronous mosfet source (connected to pgnd3). when using a current-sense resistor, connect csp3 to the pgnd3 end of the current-sense resistor. 37 csn3 controller 3 negative current-sense input. connect csn3 to the synchronous mosfet drain (connected to lx3). when using a current-sense resistor, connect csn3 to the junction of low-side mosfets source and the current-sense resistor. see figure 11. 38 bst3 controller 3 high-side gate driver supply. connect bst3 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 39 dh3 controller 3 high-side gate driver output. dh3 drives the gate of the high-side mosfet. 40 lx3 controller 3 high-side mosfet source connection/synchronous mosfet drain connection. connect the inductor and the negative side of the boost capacitor to lx3. 41 dreg3 controller 3 low-side gate driver supply. connect externally to reg and anode of the boost diode. connect a minimum of 0.1f ceramic capacitor from dreg3 to pgnd3. 42 dl3 controller 3 low-side gate driver output. dl3 is the gate driver output for the synchronous mosfet. 43 pgnd3 controller 3 power-ground connection. connect the input filter capacitors negative terminal, the source of the synchronous mosfet, and the output filter capacitors return to pgnd3. connect externally to sgnd at a single point near the input capacitor return terminal. 44 sync synchronization input. drive with a frequency at least 20% higher than three times the frequency programmed using the rt pin. the switching frequency is 1/3 the sync frequency. connect sync to sgnd when not used. 45 sgnd analog ground connection. connect sgnd and pgnd_ together at one point near the input bypass capacitor return terminal. 46 rt oscillator timing resistor connection. connect a 500k ? to 45k ? resistor from rt to sgnd to program the switching frequency from 200khz to 2.2mhz. 47 phase phase select input. connect phase to sgnd for 120 out-of-phase operation between the controllers. connect to reg for in phase operation. 48 reset reset output. open-drain reset output releases after all pgoods are released and timeout programmed by ct finishes. ep exposed pad. solder the exposed pad to a large sgnd plane.
max15003 triple-output buck controller with tracking/sequencing 13 maxim integrated functional diagrams reg v ref vr1 down1 clk1 fb1 comp1 ldo 1.24v shdn shdn res overload management vregok in sel pwm controller 1 en1 ct reset 1.24v on 1.12v off seq_ en en osc ovl config csp1 sgnd csn1 ilim1 bst1 dh1 lx1 dreg1 dl1 pgnd1 ovl_ r q set dominant s 0.925 x v ref fb1 pgpd1 pgpd_ digital soft-start and soft-stop 0.6v ref config selector e/a cpwm clk1 level shift reset timeout ramp clk2 clk3 current- limit set sync rt phase en1 ovl1 imax1 clk1 seq_ pgood1 max15003
max15003 triple-output buck controller with tracking/sequencing 14 maxim integrated detailed description the max15003 is a triple-output, pulse-width-modulat- ed (pwm), step-down, dc-dc controller with tracking and sequencing options. the device operates over the input voltage range of 5.5v to 23v or 5v 10%. each pwm controller provides an adjustable output down to 0.6v and delivers up to 15a load current with excellent load and line regulation. each of the max15003 pwm sections utilizes a volt- age-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. the device operates at a fixed switch- ing frequency that is programmable from 200khz to 2.2mhz and can be synchronized to an external clock signal using the sync input. each converter, operating at up to 2.2mhz with 120 out-of-phase, increases the input capacitor ripple frequency up to 6.6mhz, reduc- ing the rms input ripple current and the size of the input bypass capacitor requirement significantly. the max15003 provides either coincident tracking, ratiometric tracking, or sequencing. this allows tailor- ing of the power-up/power-down sequence depending on the system requirements. the max15003 features lossless valley-mode current- limit protection by monitoring the voltage drop across the synchronous mosfets on-resistance to sense the inductor current. the max15003s internal current source exhibits a positive temperature coefficient to help compensate for the mosfets temperature coefficient. use an external voltage-divider when a more precise current limit is desired. this divider along with a preci- sion shunt resistor allows for more accurate current limit. the max15003 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converters. the power-on reset ( reset ) with adjustable timeout period monitors all three outputs and provides a reset signal to a system controller/processor indicating when all outputs are within regulation. protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. functional diagrams (continued) v ref v ref vr 2/3 down2/3 clk2/3 en/ track2/3 fb2/3 comp2/3 en2/3 res overload management pwm controllers 2 and 3 en1 1.24v on 1.12v off ovl config csp2/3 csn2/3 ilim2/3 bst2/3 dh2/3 lx2/3 dreg2/3 dl2/3 pgnd2/3 ovl_ en config r q set dominant s 0.925 x v ref fb2/3 pgpd2/3 digital soft-start and soft-stop e/a cpwm clk2/3 level shift ramp current- limit set clk2/3 shdn en_ ovl2/3 imax2/3 clk2/3 seq_ seq_ pgood2/3 max15003 sel_
max15003 triple-output buck controller with tracking/sequencing 15 maxim integrated internal undervoltage lockout (uvlo) v in must exceed the default uvlo threshold before any operation can commence. the uvlo circuitry keeps the mosfet drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. the uvlo rising threshold is 4.05v with 350mv hysteresis. digital soft-start/soft-stop the max15003 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating output- voltage overshoot. soft-start begins after v in exceeds the undervoltage lockout threshold and the enable input is above 1.24v. the soft-start circuitry gradually ramps up the reference voltage. this controls the rate of rise of the output voltage and reduces input surge currents during startup. the soft-start duration is 2048 clock cycles. the output voltage is incremented through 64 equal steps. the output reaches regulation when soft-start is completed, regardless of output capacitance and load. soft-stop commences when the enable input falls below 1.12v. the soft-stop circuitry ramps down the reference voltage controlling the output voltage rate of fall. the output voltage is decremented through 64 equal steps in 2048 clock cycles. internal linear regulator (reg) reg is the output terminal of a 5v ldo powered from in that provides power to the ic. connect reg externally to dreg to provide power for the low-side mosfet gate driver. bypass reg to sgnd with a minimum 2.2f ceramic capacitor. place the capacitor physically close to the max15003 to provide good bypassing. reg is intended for powering only the internal circuitry and should not be used to supply power to external loads. reg can source up to 120ma. this current, i reg , includes quiescent current (i q ) and gate drive current (i dreg ): i reg = i q + [f sw x (q ghs_ + q gls_ )] where q ghs_ to q gls_ are the total gate charge of each of the respective high- and low-side external mosfets at v gate = 5v. f sw is the switching frequen- cy of the converter and i q is the quiescent current of the device at the switching frequency. mosfet gate drivers dreg_ is the supply input for the low-side mosfet dri- ver. connect dreg_ to reg externally. everytime the low-side mosfet switches on, high peak current is drawn from dreg for a short amount of time. adding an rc filter (1 ? to 3.3 ? and 2.2f in parallel to 0.1f ceramic capacitors are typical) from reg to dreg_ fil- ters out high-peak currents. bst_ supplies the power for the high-side mosfet dri- vers. connect the bootstrap diode from bst_ to dreg_ (anode at dreg_ and cathode at bst_). connect a bootstrap 0.1f or higher ceramic capacitor between bst_ and lx_. though not always necessary, it may be useful to insert a small resistor (4.7 ? to 22 ? ) in series with the bst_ pin and the cathode of the bootstrap diode for additional noise immunity. the high-side (dh_) and low-side (dl_) drivers drive the gates of the external n-channel mosfets. the dri- vers 2a peak source- and sink-current capability pro- vides ample drive for the fast rise and fall times of the switching mosfets. faster rise and fall times result in reduced switching losses. the gate driver circuitry also provides a break-before- make time (20ns typ) to prevent shoot-through currents during transition. oscillator/synchronization input/phase staggering (rt, sync, phase) use an external resistor at rt to program the max15003 switching frequency from 200khz to 2.2mhz. choose the appropriate resistor at rt to cal- culate the desired output switching frequency (f sw ): f sw (hz) = 10 11 /(r rt + 1750) ( ? ) connect an external clock at sync for external clock synchronization. a rising clock edge on sync is inter- preted as a synchronization input. if the sync signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by r rt . this maintains output regulation even with intermit- tent sync signals. for proper synchronization, the external frequency must be at least 20% higher than three times the frequency programmed through the rt input. the switching frequency is 1/3 the sync fre- quency. connect sync to sgnd when not used. connect phase to sgnd for 120 out-of-phase opera- tion between the controllers. connect phase to reg for in-phase operation.
max15003 triple-output buck controller with tracking/sequencing 16 maxim integrated coincident/ratiometric tracking (sel, en/track_) the enable/tracking input in conjunction with digital soft- start and soft-stop provides coincident/ratiometric track- ing (see figure 1). track an output voltage by connecting a resistive divider from the output being tracked to the enable/tracking input. for example, for v out2 to coincidentally track v out1 , connect the same resistive divider used for fb2, from out1 to en/track2 to sgnd. see figure 2 and the coincident startup and coincident shutdown graphs in the typical operating characteristics . track ratiometrically by connecting en/track_ to sgnd. this synchonizes the soft-start and soft-stop of all the controllers references, and hence their respec- tive output voltages track ratiometrically. see figure 2 and the typical operating characteristics (ratiometric startup and ratiometric shutdown graphs). connect sel to reg to configure as a triple tracker. when the max15003 converter is configured as a tracker, the output short-circuit fault situations at master or slave outputs are handled carefully so that either the master or slave output does not stay on when the other outputs are shorted to the ground. when the slave is shorted and enters in hiccup mode, both the master and the other slave soft-stop. when the master is short- ed and the part enters in hiccup mode, the slaves ratio- metrically soft-stop. coming out of the hiccup, all outputs soft-start coincidently or ratiometrically depending on their initial configuration. see the typical operating characteristics for the output behaviour dur- ing the fault conditions. during power-off, when the input falls below its uvlo, the output voltages fall down at the rate depending on the respective output capaci- tor and load. output-voltage sequencing (sel, en/track_, pgood) referring to figure 1c, when sequencing, the enable/tracking input must be above 1.24v for each pwm controller to start. the pgood_ outputs and en/track_ inputs can be daisy-chained to generate power sequenc- ing. open-drain pgood_ outputs go high impedance when fb_ is above the pgood_ threshold (555mv typ). connect a resistive divider from the power-good output to the enable/tracking input to sgnd to set when each con- troller will start. see figure 2. connect sel to sgnd to configure as a triple sequencer. v out1 v out2 v out3 v out1 v out2 v out3 v out1 v out2 v out3 soft-start soft-stop soft-start soft-stop a) coincident tracking outputs b) ratiometric tracking outputs soft- start soft-stop c) sequenced outputs figure 1. graphical representation of coincident tracking, ratiometric tracking, or pgood sequencing
max15003 triple-output buck controller with tracking/sequencing 17 maxim integrated error amplifier the output of the internal error transconductance amplifier (comp_) is provided for frequency compen- sation (see the compensation design guidelines sec- tion). the inverting input is fb_ and the output comp_. the error transamplifier has an 80db open-loop gain and a 10mhz gbw product. output short-circuit protection (hiccup mode) the current-limit circuit employs a valley current-limiting algorithm that either uses a shunt or the synchronous mosfets on-resistance as the current-sensing ele- ment. once the high-side mosfet turns off, the volt- age across the current-sensing element is monitored. if this voltage does not exceed the current-limit threshold, the high-side mosfet turns on normally at the start of the next cycle. if the voltage exceeds the current-limit threshold just before the beginning of a new pwm cycle, the controller skips that cycle. during severe overload or short-circuit conditions, the switching fre- quency of the device appears to decrease because the on-time of the low-side mosfet extends beyond a clock cycle. if the current-limit threshold is exceeded for more than eight cumulative clock cycles (n cl ), the device shuts down (both dh and dl are pulled low) for 4096 clock cycles (hiccup timeout) and then restarts with a soft- start sequence. if three consecutive cycles pass with- out a current-limit event, the count of ncl is cleared (see figure 3). hiccup mode protects against a contin- uous output short circuit. coincident tracking pgood sequencing en/track2 sel reg v in en1 ratiometric tracking r a r b r a r b r c r d v in en1 pgood1 en/track2 reg v in en1 v out2 fb2 v out3 fb3 v out1 en/track2 en/track3 r c r d en/track3 sel sel reg pgood2 en/track3 reg figure 2. ratiometric tracking, coincident tracking, pgood sequencing configurations
max15003 triple-output buck controller with tracking/sequencing 18 maxim integrated pwm controller design procedures setting the switching frequency connect a 500k ? to 45k ? resistor from rt to sgnd to program the switching frequency from 200khz to 2.2mhz. calculate the switching frequency using the following equation: f sw = 10 11 /(r rt + 1750) higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. effective input voltage range although the max15003 converters can operate from input supplies ranging from 5.5v to 23v, the input volt- age range can be effectively limited by the max15003 duty-cycle limitations for a given output voltage. the maximum input voltage is limited by the minimum on- time (t on(min) ): where t on(min) is 75ns. the minimum input voltage is limited by the maximum duty cycle and is calculated using the following equa- tion: where t off(min) typically is equal to 150ns. inductor selection three key inductor parameters must be specified for operation with the max15003: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current ( ? i p-p ). higher ? i p-p allows for a lower inductor value. a lower inductance value minimizes size and cost and improves large-signal and transient response. however, efficiency is reduced due to higher peak cur- rents and higher peak-to-peak output voltage ripple for the same output capacitor. a higher inductance increases efficiency by reducing the ripple current, however resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current lev- els especially when the inductance is increased without also allowing for larger inductor dimensions. a good rule of thumb is to choose ? i p-p equal to 30% of the full load current. calculate the inductance using the follow- ing equation: v in and v out are typical values so that efficiency is optimum for typical conditions. the switching frequen- cy is programmable between 200khz and 2.2mhz (see oscillator/synchronization input/phase staggering (rt, sync, phase) section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output current ripple is acceptable. the inductor satu- ration current (i sat ) is also important to avoid runaway current during continuous output short-circuit condi- tions. select an inductor with an i sat specification high- er than the maximum peak current. l out in out in sw p p vvv vf i = ? () ? ? v v tf in min out off min sw () () ? () 1 v v tf in max out on min sw () () current limit count of 8 n cl in clr initiate hiccup timeout n ht count of 3 n clr in clr figure 3. hiccup-mode block diagram
max15003 triple-output buck controller with tracking/sequencing 19 maxim integrated input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents, and therefore, the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage rip- ple within design requirements. the 120 ripple phase operation increases the frequency of the input capaci- tor ripple current to thrice the individual converter switching frequency. when using ripple phasing, the worst-case input capacitor ripple current is when the one converter with the highest output current is on. the input voltage ripple comprises ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of ? v q and ? v esr which peaks at the end of the on-cycle. calculate the input capacitance and esr required for a specified ripple using the following equations: where: i load(max) is the maximum output current, ? i p-p is the peak-to-peak inductor current, and f sw is the switching frequency. for the condition with only one converter is on, calculate the input ripple current using the following equation: the max15003 includes uvlo hysteresis to avoid pos- sible unintentional chattering during turn-on. use addi- tional bulk capacitance if the input source impedance is high. at lower input voltage, additional input capaci- tance helps avoid possible undershoot below the under- voltage lockout threshold during transient loading. output capacitor selection the allowed output voltage ripple and the maximum devi- ation of the output voltage during load steps determine the required output capacitance and its esr. the output ripple is mainly composed of ? v q (caused by the capaci- tor discharge) and ? v esr (caused by the voltage drop across the equivalent series resistance of the output capacitor). the equations for calculating the output capacitance and its esr are: ? v esr and ? v q are not directly additive because they are out of phase from each other. if using ceramic capacitors, which generally have low esr, ? v q domi- nates. if using electrolytic capacitors, ? v esr domi- nates. the allowable deviation of the output voltage during fast load transients also affects the output capacitance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the gain bandwidth of the converter (see the compensation design guidelines section). the resis- tive drop across the output capacitors esr, the drop across the capacitors esl, and the capacitor dis- charge cause a voltage droop during the load-step (i step ). use a combination of low-esr tantalum/alu- minum electrolytic and ceramic capacitors for better load-transient and voltage-ripple performance. surface- mount capacitors and capacitors in parallel help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. use the following equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. e esr step out step response q e esl step step v i c it v vt i sr = = sl = ? ? ? c i vf v i out pp qsw e esr pp = sr = ? ? ? ? ? ? 8 2 i vvv v cin rms i load max out in out in () () = () ? ? i vv v vf l pp in out out in sw ? ? () = e esr load max pp c in load max out in qsw v i i i v v vf sr = = ? ? ? () () + ? ? ? ? ? ? ? ? ? ? ? ? ? 2
max15003 triple-output buck controller with tracking/sequencing 20 maxim integrated setting the current limit connect a 25k ? to 150k ? resistor, r ilim , from ilim to sgnd to program the valley current-limit threshold (v cl ) from 50mv to 300mv. ilim sources 20a out to r ilim . the resulting voltage divided by 10 is the valley current-limit threshold. the max15003 uses a valley current-sense method for current limiting. the voltage drop across the low-side mosfet due to its on-resistance is used to sense the inductor current. the voltage drop (v valley ) across the low-side mosfet at the valley point and at i load is: r ds(on) is the on-resistance of the low-side mosfet, i load is the rated load current, and ? i p-p is the peak- to-peak inductor current. the r ds(on) of the mosfet varies with temperature. calculate the r ds(on) of the mosfet at its operating junction temperature at full load using the mosfet datasheet. to compensate for this temperature varia- tion, the 20a ilim reference current has a temperature coefficient of 3333ppm/c. this allows the valley cur- rent-limit threshold (v cl ) to track and partially compen- sate for the increase in the synchronous mosfets r ds(on) with increasing temperature. use the following equation to calculate r ilim : figure 4 illustrates the effect of the max15003 ilim ref- erence current temperature coefficient to compensate for the variation of the mosfet r ds(on) over the oper- ating junction temperature range. power mosfet selection when choosing the mosfets, consider the total gate charge, r ds(on) , power dissipation, the maximum drain- to-source voltage and package thermal impedance. the product of the mosfet gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. choose mosfets that are optimized for high-frequency switching applications. the average gate- drive current from the max15003s output is proportional to the frequency and gate charge required to drive the mosfet. the power dissipated in the max15003 is pro- portional to the input voltage and the average drive cur- rent (see the power dissipation section). compensation design guidelines the max15003 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by dif- ferentially comparing the sampled output voltage against a fixed reference. the subsequent error voltage that appears at the error amplifier output (comp) is compared against an internal ramp voltage to generate the required duty cycle of the pulse-width modulator. a second order lowpass lc filter removes the switching harmonics and passes the dc component of the pulse- width-modulated signal to the output. the lc filter, which has an attenuation slope of -40db/decade, intro- duces 180 of phase shift at frequencies above the lc resonant frequency. this phase shift, in addition to the inherent 180 of phase shift of the regulators self-gov- erning (negative) feedback system, poses the potential for positive feedback. the error amplifier and its associ- ated circuitry are designed to compensate for this insta- bility to achieve a stable closed-loop system. the basic regulator loop consists of a power modulator (comprises the regulators pulse-width modulator, asso- ciated circuitry, and lc filter), an output feedback divider, and an error amplifier. the power modulator has a dc gain set by v in / v ramp , with a double pole and a single zero set by the output inductance (l), the output capacitance (c out ), and its equivalent series resistance (esr). a second, higher frequency zero also exists, which is a function of the output capacitors esr and esl); though only taken into account when using very high-quality filter components and/or frequencies of operation. r ilim r ds on i cl max i pp tc = () ( ) . ? ? ? ? ? ? + ? () ? ? ? ? ? ? ? ? ?? ? 2 10 20 10 6 1 3 333 10 3 25 vr i i valley ds on load pp = () ? ? ? ? ? ? ? ? ? 2 valley current-limit threshold and r ds(on) vs. temperature max15003 fig04 temperature ( c) vi lim and r ds(on) (normalized) 130 110 70 90 -10 10 30 50 -30 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.5 -50 150 r ds(on) v ilim r ilim = 25.5k ? figure 4. current-limit trip point and v rds(on) vs. temperature
max15003 triple-output buck controller with tracking/sequencing 21 maxim integrated below are equations that define the power modulator: the switching frequency is programmable between 200khz and 2.2mhz using an external resistor at rt. typically, the crossover frequency (f co ), which is the frequency when the systems closed-loop gain is equal to unity crosses the 0db axisshould be set at or below one-tenth the switching frequency (f sw /10) for stable, closed-loop response. the max15003 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. the flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. for cost-sensitive appli- cations, use aluminum electrolytic capacitors and for space-sensitive applications, use low-esr tantalum or multilayer ceramic chip (mlcc) capacitors at the out- put. the higher switching frequencies of the max15003 allow the use of mlcc as the primary filter capacitor(s). first, select the passive and active power components that meet the applications output ripple, component size, and component cost requirements. second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below. closed-loop response and compensation of voltage-mode regulators the power modulators lc lowpass filter exhibits a vari- ety of responses, depending on the value of the l and c (and their parasitics). one such response is shown in figure 5a. in this example the power modulators uncompensated crossover is approximately 1/6 th the desired crossover frequency, f co . note also, the uncompensated roll-off through the 0db plane follows the double-pole, -40db/decade slope and approaches 180 of phase shift, indicative of a potentially unstable system. together with the inher- ent 180 of phase delay in the negative feedback system, this may lead to near 360 or positive feed- backan unstable system. the desired (compensated) roll-off follows a -20db/decade slope (and commensurate 90 of phase shift), and, in this example, occurs at approximately 6x the uncompensated crossover frequency, f co . in this example, a type ii compensator provides for stable closed-loop operation, leveraging the +20db/decade slope of the capacitors esr zero (see figure 5b). g f f f mod dc v in v ramp lc lc out zero esr esr c out zero esl esr esl () , , = = = = 1 2 1 2 2 power modulator (large, bulk output capacitor(s)) gain (real, asymptotic/ phase response vs. frequency max15003 fig05a magnitude (db) phase (degrees) -60 -40 -20 0 20 40 -80 100 1k 10k frequency (hz) 100k 1m 10m 10 -135 -90 -45 0 45 90 -180 |g mod | |g mod | f lc f zero,esl f zero,esr < g mod figure 5a. power modulator gain and phase response (large, bulk c out ) max15003 fig05b magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 60 80 -80 -135 -90 -45 0 45 90 135 180 -180 power modulator (large, bulk output capacitor(s)) and type ii compensation gain (asymptotic)/phase response vs. frequency 100 1k 10k 100k 1m 10m 10 max15003 triple-output buck controller with tracking/sequencing 22 maxim integrated the type ii compensators mid-frequency gain (approximately 18db shown here) is designed to com- pensate for the power modulators attenuation at the desired crossover frequency, f co (g e/a + g mod = 0db at f co ). in this example, the power modulators inherent -20db/decade roll-off above the esr zero (f zero, esr ) is leveraged to extend the active regulation gain-band- width of the voltage regulator. as shown in figure 5b, the net result is a 6x increase in the regulators gain bandwidth while providing greater than 75 of phase margin (the difference between g e/a and g mod respective phases at crossover, f co ). other filter schemes pose their own problems. for instance, when choosing high-quality filter capacitor(s), e.g., mlccs, and an inductor with minimal parasitics, the inherent esr zero may occur at a much higher fre- quency, as shown in figure 5c. as with the previous example, the actual gain and phase response is overlaid on the power modulators asymptotic gain response. one readily observes the more dramatic gain and phase transition at or near the power modulators resonant frequency, f lc , versus the gentler response of the previous example. this is due to the components lower parasitics leading to the high- er frequency of the inherent esr zero of the output capacitor. in this example, the desired crossover fre- quency occurs below the esr zero frequency. in this example, a compensator with an inherent mid- frequency double-zero response is required to mitigate the effects of the filters double-pole. such is available with the type iii topology. as demonstrated in figure 5d, the type iiis mid- frequency double-zero gain (exhibiting a +20db/ decade slope, noting the compensators pole at the ori- gin) is designed to compensate for the power modula- tors double-pole -40db/decade attenuation at the desired crossover frequency, f co (again, g e/a + g mod = 0db at f co ). (see figure 5d). in the above example, the power modulators inherent (mid-frequency) -40db/decade roll-off is mitigated by the mid-frequency double zeros +20db/decade gain to extend the active regulation gain-bandwidth of the volt- age regulator. as shown in figure 5d, the net result is an approximate doubling in the regulators gain band- width while providing greater than 60 of phase margin (the difference between g e/a and g mod respective phases at crossover, f co ). design procedures for both type ii and type iii com- pensators are shown below. magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 -80 -135 -90 -45 0 45 90 -180 power modulator (high-quality output capacitors (s)) gain (real, asymptotic)/ phase response vs. frequency max15003 fig05c 100 1k 10k 100k 1m 10m 10 |g mod | |g mod | |g mod | f lc f zeroes f zeroes figure 5c. power modulator gain and phase response (high- quality c out ) power modulator (high-quality output capacitor(s)) and type iii compensator gain (asymptotic)/ phase response vs. frequency max15003 fig05d magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 60 80 -80 -203 -135 -68 0 68 135 203 270 -270 100 1k 10k 100k 1m 10m 10 < g ea |g ea | |g mod | f lc f zeroes f zeroes f co < g mod figure 5d. power modulator (high-quality c out ) and type iii compensator responses
max15003 triple-output buck controller with tracking/sequencing 23 maxim integrated type ii: compensation when f co > f zero, esr when the f zero,esr is lower than f co and close to f lc , a type ii compensation network provides the neces- sary closed-loop response. the type ii compensation network provides a mid-band compensating zero and high-frequency pole (see figures 6a and 6b). r f c f provides the mid-band zero f mid,zero , and r f c cf provides the high-frequency pole. use the fol- lowing procedure to calculate the compensation net- work components. 1) calculate the f zero,esr and lc double pole, f lc : 2) calculate the unity-gain crossover frequency as: 3) determine r f from the following: note: r f is derived by setting the total loop gain at crossover frequency to unity, e.g., g ea (f co ) x g m (f co ) = 1v/v. the transconductance error amplifier gain is g ea (f co ) = g m x r f while the modulator gain is: the total loop gain can be expressed logarithmically as follows: where v ramp is the peak-to-peak ramp amplitude equal to 2v. 4) place a zero at or below the lc double pole, f lc : 5) place a high-frequency pole at or below f p = 0.5 x f sw : 6) choose an appropriately sized r1 (connected from out_ to fb_, start with a 10k ? ). once r1 is select- ed, calculate r2 using the following equation: where v fb = 0.6v. r r v fb v out v fb 21 = ? c cf r f f sw = 1 c f r f f lc = 1 2 2 2 2 0 0log 10 g m r f + 0log 10 [] () ? ? ? ? ? ? ? ? = esr v in v fb f co lv out v ramp db gf mod co v in v ramp esr f co l v fb v out () = 2 r f v ramp f co lv out v fb v in g m esr = () 2 f co f sw 10 f f zero esr esr c out lc lc out , = = 1 2 1 2 r 1 r f comp v out v ref c cf c f r 2 - + g m figure 6a. type ii compensation network gain (db) 1st asymptote g mod v ref v out -1 ( c f ) -1 (rad/s) 3rd asymptote g mod v ref v out -1 ( c cf ) -1 2nd asymptote g mod v ref v out -1 r f 1st pole (at origin) 2nd pole (r f c cf ) -1 1st zero (r f c f ) -1 figure 6b. type ii compensation network response
max15003 triple-output buck controller with tracking/sequencing 24 maxim integrated type iii: compensation when f co < f zero, esr as indicated above, the position of the output capaci- tors inherent esr zero is critical in designing an appro- priate compensation network. when low-esr ceramic output capacitors are used, the esr zero frequency (f zero, esr ) is usually much higher than unity crossover frequency (f co ). in this case, a type iii com- pensation network is recommended (see figure 7a). as shown in figure 7b, a type iii compensation net- work introduces two zeros and three poles into the con- trol loop. the error amplifier has a low-frequency pole at the origin, two zeros, and higher frequency poles. the locations of the zeros and poles should be such that the phase margin peaks at f co . set the ratios of f co -to-f z and f p -to-f co equal to one another, e.g., f co = f p = 5 is a good number to get about f z f co 60 of phase margin at f co . whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. use the following procedure to calculate the compen- sation network components. 1) select a crossover frequency, f co : 2) calculate the lc double-pole frequency, f lc : 3) select r f 10k ? . 4) place a zero f z1 = 1 at 0.75 x f lc where 2 x r f x c f 5) calculate c i for a target unity-gain crossover fre- quency, f c : note: c i is derived by setting the total loop gain at crossover frequency to unity, e.g., g ea (f co ) x g mod (f co ) = 1v/v. the total loop gain can be expressed logarithmically as follows: 6) place a second zero, f z2 , at or below f lc thereby determining r 1 . 7) place a pole (f p1 = 1 ), at or below f zero,esr . (2 x r 1 x c i ) 8) place a second pole (f p2 = 1 ) at or below 2 x r f x c cf one-half the switching frequency. 9) calculate r2 using the following equation: where v fb = 0.6v. rr v fb v out v fb 21 = ? c cf f sw r f = 1 r f zero esr c i 1 1 2 = , r f z c i 1 1 2 2 = 20 2 20 2 0 10 10 2 [] + () ? ? ? ? ? ? ? ? = log log () frc g flc db co f i mod dc co out c i f co lc out v ramp v in r f = 2 c f r f f lc = 1 2075 . f lc lc out = 1 2 f co f sw 10 r1 r f comp v out v ref r2 r i c i c f c cf - + g m figure 7a. type iii compensation network figure 7b. type iii compensation network response gain (db) 1st asymptote ( r i c f ) -1 3rd asymptote r f c i 5th asymptote ( r i c cf ) -1 4th asymptote r f r i -1 (rad/sec) 2nd asymptote (r f r i ) -1 1st pole (at origin) 2nd pole (r i c i ) -1 3rd pole (r f c cf ) -1 1st zero (r f c f ) -1 2nd zero (r i c i ) -1
max15003 triple-output buck controller with tracking/sequencing 25 maxim integrated typical operating circuits max15003 dreg3 vout2 150 f/16v 19.1k ? 6.04k ? 750 ? 10k ? 100 f 0.1 f 3.3 f 22 f 0.1 f 25.5k ? 1.8 f 11k ? 2.2 f 470nf 11k ? 25.5k ? 165k ? 10k ? 2.2 f 0.022 f 470pf 1.2nf 47pf 13k ? 25.5k ? 4.22k ? 19.1k ? 10k ? 750k ? 1800pf 47pf 1200nf 100 f 34k ? 34k ? 1.15k ? 10k ? 0.1 f 22 f 1nf 47pf 100nf 2.2 ? 2.2 ? ( 1 / 2 ) irf7904 ( 1 / 2 ) fds6982a5 ( 1 / 2 ) fds6982a5 irf7807z ntmfs4835n in c in pgnd sgnd bst3 dh3 lx3 csn3 c out 120 f (2) dl3 vout3 csp3 pgnd3 ep en/track3 fb3 comp3 ilim3 pgood3 in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 8. coincident triple tracker with lossless current sense
max15003 triple-output buck controller with tracking/sequencing 26 maxim integrated typical operating circuits (continued) max15003 dreg3 vout2 in c in pgnd sgnd bst3 dh3 lx3 csn3 c out dl3 vout3 csp3 pgnd3 ep en/track3 fb3 comp3 ilim3 pgood3 in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 9. triple sequencer with lossless current sense
max15003 triple-output buck controller with tracking/sequencing 27 maxim integrated typical operating circuits (continued) max15003 dreg3 vout2 in c in pgnd sgnd bst3 dh3 lx3 csn3 c out dl3 vout3 csp3 pgnd3 ep en/track3 fb3 comp3 ilim3 pgood3 in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 10. coincident dual tracker and a sequencer with lossless current sense
max15003 triple-output buck controller with tracking/sequencing 28 maxim integrated typical operating circuits (continued) max15003 dreg3 vout2 in c in pgnd sgnd bst3 dh3 lx3 dl3 c out csn3 vout3 csp3 pgnd3 ep en/track3 fb3 comp3 ilim3 pgood3 in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 11. ratiometric triple tracker with accurate valley-mode current sense
max15003 triple-output buck controller with tracking/sequencing 29 maxim integrated pwm controller applications information power dissipation the 48-pin tqfn thermally enhanced package can dis- sipate up to 3.08w. calculate power dissipation in the max15003 as a product of the input voltage and the total reg output current (i reg ). i reg includes quies- cent current (i q ) and the total gate drive current (i dreg ): p d = v in x i reg i reg = i q + [f sw x (q g1 + q g2 + q g3 + q g4 + q g5 + q g6 )] where q g1 to q g6 are the total gate charge of the low- side and high-side external mosfets. f sw is the switching frequency of the converter and i q is the qui- escent current of the device at the switching frequency. use the following equation to calculate the maximum power dissipation (p dmax ) in the chip at a given ambi- ent temperature (t a ): p dmax = 38.5 x (150 - t a ).mw pcb layout guidelines use the following guidelines to layout the switching voltage regulator. 1) place the in, reg, and dreg_ bypass capacitors close to the max15003. 2) minimize the area and length of the high-current loops from the input capacitor, upper switching mosfet, inductor, and output capacitor back to the input capacitor negative terminal. 3) keep the current loop formed by the lower switch- ing mosfet, inductor, and output capacitor short. 4) keep sgnd and pgnd isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) run the current-sense lines csp_ and csn_ close to each other to minimize the loop area. 6) avoid long traces between the dreg_ bypass capacitor, low-side driver outputs of the max15003, mosfet gate, and pgnd. minimize the loop formed by the dreg_ bypass capacitor, bootstrap diode, bootstrap capacitor, high-side dri- ver output of the max15003, and upper mosfet gates. 7) place the bank of output capacitors close to the load. 8) distribute the power components evenly across the board for proper heat dissipation. 9) provide enough copper area at and around the switching mosfets, and inductor to aid in thermal dissipation. 10) connect the max15003 exposed paddle to a large copper plane to maximize its power dissipation capability. connect the exposed paddle to sgnd. do not connect the exposed paddle to the sgnd pin (pin 45) directly underneath the ic. 11) use 2oz copper to keep the trace inductance and resistance to a minimum. thin copper pcbs com- promise efficiency because high currents are involved in the application. also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
max15003 triple-output buck controller with tracking/sequencing 30 maxim integrated chip information process: bicmos top view max15003 thin qfn (7mm x 7mm) 13 14 15 16 17 18 19 20 21 22 23 24 ilim1 comp1 en1 fb1 pgood1 pgnd2 dl2 dreg2 lx2 dh2 bst2 csn2 48 47 46 45 44 43 42 41 40 39 38 37 1 + 2 345 678910 11 12 reset phase rt sgnd sync pgnd3 dl3 dreg3 lx3 dh3 bst3 csn3 csp1 csn1 bst1 dh1 lx1 dreg1 dl1 pgnd1 sel reg in ct 36 35 34 33 32 31 30 29 28 27 26 25 csp2 ilim2 comp2 en/track2 fb2 pgood2 pgood3 fb3 en/track3 comp3 ilim3 csp3 pin configuration package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 48 tqfn-ep t4877+3 21-0144 90-0129
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 31 ? 2012 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. max15003 triple-output buck controller with tracking/sequencing revision history revision number revision date description pages changed 0 10/07 initial release 1 8/12 updated mosfet gate drivers section 15

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